Flash memory is a non-volatile memory, i.e. flash memory can retain a state even without power supply. Flash memory stores a state based on the changes in the threshold voltage (VT) of a floating gate metal oxide semiconductor (MOS) transistor. Flash test (testing of flash memory) therefore needs to characterize the threshold voltage and associated bit cell current (BCC) of each flash bit in the design. Characterization involves measuring variations or shifts in the threshold voltage (VT) and bit cell current (BCC) due to each of current (I), voltage (V) and temperature (T) stress application. The number of I, V and T stress conditions for the flash bit are many and are required to screen reliability of a floating gate flash bit. Due to this requirement, a large number of read operations need to be performed per search cycle for each stress condition.
Flash access time is much slower compared to an equivalent static random access memory (SRAM) access time requiring higher test time per read iteration. Flash core architecture is different from the SRAM because the operations such as program or erase can require multiple attempts for the bit cell to store data robustly. With development in technology, on chip flash has increased over 4 times in 65 nm CMOS manufacturing process compared to prior technologies causing flash test time to become 80% of device test time. As such, there is a need for a solution that restricts the linear increase in test time with increasing flash size.